.nolist ;******************************************************************************************************************************** ;* * ;* File: PM.inc * ;* * ;* This file contains constants and structures related to Protected Mode. * ;* * ;* It cannot be included more than once, otherwise errors result. * ;* * ;* It was written for MASM, but shouldn't be too difficult to adapt for other assemblers. * ;* * ;* The main source of information for this is the IA-32 Intel Software Developer's Manual Volume 3: System Programming Guide. * ;* * ;* Authors: * ;* - Neil G. Dickson * ;* * ;******************************************************************************************************************************** CR0_PAGING_BIT equ 10000000000000000000000000000000b CR0_CACHE_DISABLE_BIT equ 01000000000000000000000000000000b CR0_NOT_WRITE_THROUGH_BIT equ 00100000000000000000000000000000b CR0_ALIGNMENT_MASK_BIT equ 00000000000001000000000000000000b CR0_WRITE_PROTECT_BIT equ 00000000000000010000000000000000b CR0_NUMERIC_ERROR_BIT equ 00000000000000000000000000100000b CR0_EXTENTION_TYPE_BIT equ 00000000000000000000000000010000b ;hard-coded to 1 on Pentium 2 and beyond CR0_SET_BIT equ 00000000000000000000000000010000b ;so define it as a set bit too CR0_TASK_SWITCHED_BIT equ 00000000000000000000000000001000b CR0_EMULATION_BIT equ 00000000000000000000000000000100b CR0_MONITOR_COPROCESSOR_BIT equ 00000000000000000000000000000010b CR0_PROTECTION_BIT equ 00000000000000000000000000000001b CR3_PAGE_CACHE_DISABLE_BIT equ 00000000000000000000000000010000b CR3_PAGE_WRITE_THROUGH_BIT equ 00000000000000000000000000001000b CR4_V86_EXTENTIONS_BIT equ 00000000001b CR4_PM_VINT_BIT equ 00000000010b CR4_TIME_STAMP_DISABLE_BIT equ 00000000100b CR4_DEBUG_EXTENTIONS_BIT equ 00000001000b CR4_PAGE_SIZE_EXTENTION_BIT equ 00000010000b CR4_ADDRESS_EXTENTION_BIT equ 00000100000b CR4_MACHINE_CHK_ENABLE_BIT equ 00001000000b CR4_PAGE_GLOBAL_ENABLE_BIT equ 00010000000b CR4_PMC_ENABLE_BIT equ 00100000000b ;performance monitor counter enabling CR4_OSFXSR_BIT equ 01000000000b CR4_OSXMMEXCPT_BIT equ 10000000000b EFLAGS_CARRY_FLAG equ 00000000000000000000000000000001b EFLAGS_SET_BIT equ 00000000000000000000000000000010b EFLAGS_PARITY_FLAG equ 00000000000000000000000000000100b EFLAGS_AUXILIARY_CARRY_FLAG equ 00000000000000000000000000010000b EFLAGS_ZERO_FLAG equ 00000000000000000000000001000000b EFLAGS_SIGN_FLAG equ 00000000000000000000000010000000b EFLAGS_TRAP_FLAG equ 00000000000000000000000100000000b EFLAGS_INT_ENABLE_FLAG equ 00000000000000000000001000000000b EFLAGS_DIRECTION_FLAG equ 00000000000000000000010000000000b EFLAGS_OVERFLOW_FLAG equ 00000000000000000000100000000000b EFLAGS_IOPL_BITS equ 00000000000000000011000000000000b EFLAGS_NESTED_TASK_FLAG equ 00000000000000000100000000000000b EFLAGS_RESUME_FLAG equ 00000000000000010000000000000000b EFLAGS_V86_MODE_FLAG equ 00000000000000100000000000000000b EFLAGS_ALIGN_CHECK_FLAG equ 00000000000001000000000000000000b EFLAGS_VINT_FLAG equ 00000000000010000000000000000000b EFLAGS_VINT_PENDING_FLAG equ 00000000000100000000000000000000b EFLAGS_IDENTIFICATION_FLAG equ 00000000001000000000000000000000b EFLAGS_ADJUST_FLAG equ EFLAGS_AUXILIARY_CARRY_FLAG PAGE_PRESENT_BIT equ 0000000000001b PAGE_WRITABLE_BIT equ 0000000000010b PAGE_USER_BIT equ 0000000000100b PAGE_WRITE_THROUGH_BIT equ 0000000001000b PAGE_CACHE_DISABLE_BIT equ 0000000010000b PAGE_ACCESSED_BIT equ 0000000100000b ;if page or page table read from PAGE_DIRTY_BIT equ 0000001000000b ;if page written to PAGE_SIZE_BIT equ 0000010000000b PAGE_TABLE_ATTRIBUTE_INDEX equ 0000010000000b PAGE_GLOBAL_BIT equ 0000100000000b ;must set CR4_PAGE_GLOBAL_ENABLE_BIT, reserved on Pentium PAGE_AVAILABLE_BITS equ 0111000000000b PAGE_TABLE_ATTRIBUTE_INDEX4M equ 1000000000000b SELECT_REQ_PRIV_LEVEL_BITS equ 011b SELECT_TABLE_INDICATOR_BIT equ 100b DESC_NOT_SYSTEM_BIT equ 00010000b ;byte 5 DESC_CODE_BIT equ 00001000b ;byte 5 DESC_D_EXPAND_DOWN_BIT equ 00000100b ;byte 5 DESC_D_WRITABLE_BIT equ 00000010b ;byte 5 DESC_D_ACCESSED_BIT equ 00000001b ;byte 5 DESC_C_CONFORMING_BIT equ 00000100b ;byte 5 DESC_C_READABLE_BIT equ 00000010b ;byte 5 DESC_C_ACCESSED_BIT equ DESC_D_ACCESSED_BIT ;byte 5 DESC_ACCESSED_BIT equ DESC_D_ACCESSED_BIT ;byte 5 DESC_S_TSS_AVL_16 equ 00000001b ;byte 5 DESC_S_LDT equ 00000010b ;byte 5 DESC_S_TSS_BSY_16 equ 00000011b ;byte 5 DESC_S_CALL_GATE_16 equ 00000100b ;byte 5 DESC_S_TASK_GATE equ 00000101b ;byte 5 DESC_S_INT_GATE_16 equ 00000110b ;byte 5 DESC_S_TRAP_GATE_16 equ 00000111b ;byte 5 DESC_S_TSS_AVL_32 equ 00001001b ;byte 5 DESC_S_TSS_BSY_32 equ 00001011b ;byte 5 DESC_S_CALL_GATE_32 equ 00001100b ;byte 5 DESC_S_INT_GATE_32 equ 00001110b ;byte 5 DESC_S_TRAP_GATE_32 equ 00001111b ;byte 5 DESC_S_TSS_BSY_BIT equ 00000010b ;byte 5 DESC_PRIV_LEVEL_BITS equ 01100000b ;byte 5 DESC_PRIV_LEVEL0 equ 00000000b ;byte 5 DESC_PRIV_LEVEL1 equ 00100000b ;byte 5 DESC_PRIV_LEVEL2 equ 01000000b ;byte 5 DESC_PRIV_LEVEL3 equ 01100000b ;byte 5 DESC_PRESENT_BIT equ 10000000b ;byte 5 DESC_AVAILABLE_BIT equ 00010000b ;byte 6 DESC_SIZE_BIT equ 01000000b ;byte 6 DESC_GRANULARITY_BIT equ 10000000b ;byte 6 INT_DIVIDE_ERROR equ 00h INT_DEBUG_EXCEPTION equ 01h INT_NONMASKABLE_INTERRUPT equ 02h INT_BREAKPOINT equ 03h INT_OVERFLOW_EXCEPTION equ 04h INT_BOUND_RANGE_EXCEPTION equ 05h INT_INVALID_OPCODE equ 06h INT_DEVICE_NOT_AVAILABLE equ 07h INT_DOUBLE_FAULT equ 08h INT_COPROC_SEGMENT_OVERRUN equ 09h ;only on 386/387 INT_INVALID_TSS equ 0Ah INT_SEGMENT_NOT_PRESENT equ 0Bh INT_STACK_FAULT equ 0Ch INT_GENERAL_PROTECTION equ 0Dh INT_PAGE_FAULT equ 0Eh INT_FP_EXCEPTION equ 0Fh INT_ALIGNMENT_CHECK equ 10h INT_MACHINE_CHECK equ 11h INT_SIMD_FP_EXCEPTION equ 12h INT_USER_DEF equ 20h TSS32 STRUCT PrevTaskLink WORD ? WORD ? rESP0 DWORD ? rSS0 WORD ? WORD ? rESP1 DWORD ? rSS1 WORD ? WORD ? rESP2 DWORD ? rSS2 WORD ? WORD ? rCR3 DWORD ? ;(CR3 a.k.a. Page Directory Base Register) rEIP DWORD ? rEFLAGS DWORD ? rEAX DWORD ? rECX DWORD ? rEDX DWORD ? rEBX DWORD ? rESP DWORD ? rEBP DWORD ? rESI DWORD ? rEDI DWORD ? rES WORD ? WORD ? rCS WORD ? WORD ? rSS WORD ? WORD ? rDS WORD ? WORD ? rFS WORD ? WORD ? rGS WORD ? WORD ? LDTSeg WORD ? WORD ? DebugTrap WORD ? ;(only first bit) exception raised if switch to this task when set IOMapBase WORD ? ;indicates offset from base of TSS of I/O permission bit map ;and ending offset of interrupt redirection bit map ;none if at or past TSS segment limit TSS32 ENDS FSTENVSTATE32 STRUCT ;different in 16-bit PM (or size prefix in 32-bit PM), in Real Mode, and with size prefix in Real Mode: 4 types in all ControlWord WORD ? WORD ? StatusWord WORD ? WORD ? TagWord WORD ? WORD ? InstructionPointer DWORD ? InstructionSelector WORD ? Opcode WORD ? ;only lower bit0-bit10 used, other 5 are 0, and usually not used on Pentium4 unless in FOpcode Compatibility Mode OperandPointer DWORD ? OperandSelector WORD ? WORD ? FSTENVSTATE32 ENDS FSAVESTATE32 STRUCT ControlWord WORD ? WORD ? StatusWord WORD ? WORD ? TagWord WORD ? WORD ? InstructionPointer DWORD ? InstructionSelector WORD ? Opcode WORD ? ;only lower bit0-bit10 used, other 5 are 0, and usually not used on Pentium4 unless in FOpcode Compatibility Mode OperandPointer DWORD ? OperandSelector WORD ? WORD ? rST0 REAL10 ? rST1 REAL10 ? rST2 REAL10 ? rST3 REAL10 ? rST4 REAL10 ? rST5 REAL10 ? rST6 REAL10 ? rST7 REAL10 ? FSAVESTATE32 ENDS ifndef DQWORD DQWORD STRUCT Dwords dword 4 dup (?) DQWORD ENDS endif FXSAVESTATE32 STRUCT ;different in 16-bit PM (or size prefix in 32-bit PM), in Real Mode, and with size prefix in Real Mode: 4 types in all ;must be 16-byte aligned ControlWord WORD ? StatusWord WORD ? CompactTagWord BYTE ? ;set bits indicate valid (00b), zero (01b), or special (10b), clear bits indicate empty (11b) BYTE ? Opcode WORD ? ;only lower bit0-bit10 used, other 5 are 0, and usually not used on Pentium4 unless in FOpcode Compatibility Mode InstructionPointer DWORD ? InstructionSelector WORD ? WORD ? OperandPointer DWORD ? OperandSelector WORD ? WORD ? rMXCSR DWORD ? MXCSRMask DWORD ? rST0 REAL10 ? FWORD ? rST1 REAL10 ? FWORD ? rST2 REAL10 ? FWORD ? rST3 REAL10 ? FWORD ? rST4 REAL10 ? FWORD ? rST5 REAL10 ? FWORD ? rST6 REAL10 ? FWORD ? rST7 REAL10 ? FWORD ? rXMM0 DQWORD <> rXMM1 DQWORD <> rXMM2 DQWORD <> rXMM3 DQWORD <> rXMM4 DQWORD <> rXMM5 DQWORD <> rXMM6 DQWORD <> rXMM7 DQWORD <> DQWORD 14 dup (<>) FXSAVESTATE32 ENDS ;**************************************************** ;* CPUID * ;**************************************************** CPUID_FN_FEATURES equ 1 ;function returns feature information and processor model CPUID_EDX_FPU equ 00000001h ;presence of FPU CPUID_EDX_TSC equ 00000010h ;TSC support (RDTSC) CPUID_EDX_MSR equ 00000020h ;MSR support (RDMSR/WRMSR) CPUID_EDX_APIC equ 00000200h ;presence of APIC CPUID_EDX_MTRR equ 00001000h ;MTRR support CPUID_EDX_PTE_GLOBAL equ 00002000h ;PTE and PDE global bit support CPUID_EDX_CMOV equ 00008000h ;CMOVcc instruction support CPUID_EDX_PAT equ 00010000h ;PAT support CPUID_EDX_MMX equ 00800000h ;MMX support CPUID_EDX_FXSAVE equ 01000000h ;FXSAVE/FXRSTOR CPUID_EDX_SSE equ 02000000h ;SSE support CPUID_EDX_SSE2 equ 04000000h ;SSE2 support CPUID_EDX_HTT equ 10000000h ;HTT support ;**************************************************** ;* MODEL-SPECIFIC REGISTERS * ;* (others are in related sections) * ;**************************************************** MSR_SYSENTER_CS equ 174h MSR_SYSENTER_ESP equ 175h MSR_SYSENTER_EIP equ 176h ;**************************************************** ;* MEMORY TYPE RANGE REGISTERS * ;**************************************************** MSR_MTRRCAP equ 0FEh MSR_MTRR_DEF_TYPE equ 2FFh MSR_MTRR_PHYSBASE0 equ 200h MSR_MTRR_PHYSMASK0 equ 201h MSR_MTRR_PHYSBASE1 equ 202h MSR_MTRR_PHYSMASK1 equ 203h MSR_MTRR_PHYSBASE2 equ 204h MSR_MTRR_PHYSMASK2 equ 205h MSR_MTRR_PHYSBASE3 equ 206h MSR_MTRR_PHYSMASK3 equ 207h MSR_MTRR_PHYSBASE4 equ 208h MSR_MTRR_PHYSMASK4 equ 209h MSR_MTRR_PHYSBASE5 equ 20Ah MSR_MTRR_PHYSMASK5 equ 20Bh MSR_MTRR_PHYSBASE6 equ 20Ch MSR_MTRR_PHYSMASK6 equ 20Dh MSR_MTRR_PHYSBASE7 equ 20Eh MSR_MTRR_PHYSMASK7 equ 20Fh MSR_PAT equ 277h MTRR_MASK_VALID equ 800h MEM_UNCACHEABLE equ 0 MEM_WRITE_COMBINING equ 1 MEM_WRITE_THROUGH equ 4 MEM_WRITE_PROTECTED equ 5 MEM_WRITEBACK equ 6 MEM_UNCACHED equ 7 ;**************************************************** ;* APIC * ;**************************************************** OFFSET_APIC equ 0FEE00000h ;Normal Local APIC Base (but can be different) LOCALAPICMEM STRUCT dword 4 dup (?) dword 4 dup (?) APICIDReg dword 4 dup (?) VersionReg dword 4 dup (?) ;read-only dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) TaskPriorityReg dword 4 dup (?) ArbitirationReg dword 4 dup (?) ;read-only ;Arbitration Priority Register: not supported on P4 ProcessorPriorityReg dword 4 dup (?) ;read-only EndOfIntReg dword 4 dup (?) ;write-only: write 0 to indicate end of int for all but ExtINT, INIT, SIPI, NMI, SMI, INIT-Deassert delivery modes, and also not Spurious Int dword 4 dup (?) LogicalDestReg dword 4 dup (?) DestFormatReg dword 4 dup (?) ;bits 0-27 read-only, bits 28-31 read/write SpuriousIntVectorReg dword 4 dup (?) ;bits 0-8 read/write, bits 9-31 read-only InServiceReg dword 4 dup (?) ;read-only, dword0 dword 4 dup (?) ;read-only, dword1 dword 4 dup (?) ;read-only, dword2 dword 4 dup (?) ;read-only, dword3 dword 4 dup (?) ;read-only, dword4 dword 4 dup (?) ;read-only, dword5 dword 4 dup (?) ;read-only, dword6 dword 4 dup (?) ;read-only, dword7 TriggerModeReg dword 4 dup (?) ;read-only, dword0 dword 4 dup (?) ;read-only, dword1 dword 4 dup (?) ;read-only, dword2 dword 4 dup (?) ;read-only, dword3 dword 4 dup (?) ;read-only, dword4 dword 4 dup (?) ;read-only, dword5 dword 4 dup (?) ;read-only, dword6 dword 4 dup (?) ;read-only, dword7 IntRequestReg dword 4 dup (?) ;read-only, dword0 dword 4 dup (?) ;read-only, dword1 dword 4 dup (?) ;read-only, dword2 dword 4 dup (?) ;read-only, dword3 dword 4 dup (?) ;read-only, dword4 dword 4 dup (?) ;read-only, dword5 dword 4 dup (?) ;read-only, dword6 dword 4 dup (?) ;read-only, dword7 ErrorStatusReg dword 4 dup (?) ;read-only dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) IntCommandReg dword 4 dup (?) ;dword0 dword 4 dup (?) ;dword1 LVTTimerReg dword 4 dup (?) LVTThermalSensorReg dword 4 dup (?) LVTPerformanceReg dword 4 dup (?) ;Performance Monitoring Counter Register: may not be present in future processors LVTLINT0Reg dword 4 dup (?) LVTLINT1Reg dword 4 dup (?) LVTErrorReg dword 4 dup (?) TimerInitialCountReg dword 4 dup (?) TimerCurrentCountReg dword 4 dup (?) ;read-only dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) dword 4 dup (?) TimerDivideConfigReg dword 4 dup (?) dword 4 dup (?) LOCALAPICMEM ENDS OFFSET_APIC_ID equ 0FEE00020h ;Processor's Local APIC ID stored in high byte. Same as CPUID function 1 EBX. OFFSET_APIC_VERSION equ 0FEE00030h OFFSET_APIC_EOI equ 0FEE000B0h ;End Of Interrupt register OFFSET_APIC_SVR equ 0FEE000F0h ;Spurious-Interrupt Vector Register, also contains APIC enable bit OFFSET_APIC_ICR1 equ 0FEE00300h ;if using ICR2, ICR1 must be written-to last (writing to it issues the interrupt) APIC_ICR1_INIT equ 000000500h ;INIT IPI APIC_ICR1_STARTUP equ 000000600h ;Start-up IPI APIC_ICR1_SEND_PENDING equ 000001000h ;Read-only, indicates that the APIC is stil waiting to dispatch the IPI APIC_ICR1_SET_BIT equ 000004000h ;Level (assert/de-assert) flag, but obsolete on Pentium4, must be set APIC_ICR1_LEVEL_TRIGGER equ 000008000h ;Edge triggered if clear, level triggered if set APIC_ICR1_SELF equ 000040000h ;IPI to sending processor ;if one of these 3 used, don't have to set ICR2 for destination APIC_ICR1_ALL equ 000080000h ;IPI to all processors (including self) ;otherwise high byte of ICR2 has destination APIC ID APIC_ICR1_ALL_BUT_SELF equ 0000C0000h ;IPI to all processors excluding self ; OFFSET_APIC_ICR2 equ 0FEE00310h OFFSET_APIC_LVT_TIMER equ 0FEE00320h ;timer interrupt (and possibly other LVT interrupts) are blocked/unblocked with cli/sti (or by explicitly masking them individually) OFFSET_APIC_LVT_ERROR equ 0FEE00370h OFFSET_APIC_TIMER_INITIAL equ 0FEE00380h OFFSET_APIC_TIMER_CURRENT equ 0FEE00390h ;timer interrupt sent when this reaches 0, but writing 0 to this will end the timer without sending an interrupt OFFSET_APIC_TIMER_DIVIDE equ 0FEE003E0h APIC_TIMER_DIVIDE_2 equ 000000000h ;default is 2 APIC_TIMER_DIVIDE_4 equ 000000001h APIC_TIMER_DIVIDE_8 equ 000000002h APIC_TIMER_DIVIDE_16 equ 000000003h APIC_TIMER_DIVIDE_32 equ 000000008h APIC_TIMER_DIVIDE_64 equ 000000009h APIC_TIMER_DIVIDE_128 equ 00000000Ah APIC_TIMER_DIVIDE_1 equ 00000000Bh APIC_SVR_ENABLE_BIT equ 000000100h ;enables APIC MSR_APIC_BASE equ 1Bh OFFSET_IOAPIC equ 0FEC00000h ;Normal I/O APIC Base (but can be different) OFFSET_IOAPIC_REGSEL equ 0FEC00000h ;Default, changes when MSR_APIC_BASE is changed by software OFFSET_IOAPIC_DATA equ 0FEC00010h IOAPIC_REG_ID equ 0h IOAPIC_REG_VERSION equ 1h IOAPIC_REG_ARB_ID equ 2h IOAPIC_REG_IRQ equ 10h IOAPIC_NUM_IRQS equ 18h IOAPIC_IRQ_LOW_ACTIVE equ 000002000h ;usually set for IRQ16-19 ;clear is high active, usually for IRQ0-15 ;unsure on usual for IRQ20-23 IOAPIC_IRQ_LEVEL_TRIGGERED equ 000008000h ;usually set for IRQ16-19 ;clear is edge-triggered, usually for IRQ0-15 ;unsure on usual for IRQ20-23 IOAPIC_IRQ_MASK_BIT equ 000010000h .list